Graphical Framework for Automatic Generation of Custom UVM Testbenches in SystemVerilog Applied for the Validation of a SerDes DUT /

Antzeko izenburuak

• Writing Testbenches Using SystemVerilog /
  nork: Bergeron, Janick
  Argitaratua: (2006, c2006)
• Logic Design and Verification Using SystemVerilog /
  nork: Thomas, Donald E.
  Argitaratua: (2014, c2014)
• SystemVerilog Assertions and Functional Coverage : Guide to Language, Methodology and Applications /
  nork: Mehta, Ashok B.
  Argitaratua: (2020, c2020)
• SystemVerilog for Hardware Description : RTL Design and Verification /
  nork: Taraate, Vaibbhav
  Argitaratua: (2020, c2020)
• Verilog for Example : A Concise Introduction for FPGA Design /
  nork: Readler, Blaine C.
  Argitaratua: (2011, c2011)