Graphical Framework for Automatic Generation of Custom UVM Testbenches in SystemVerilog Applied for the Validation of a SerDes DUT /

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• SystemVerilog Assertions and Functional Coverage : Guide to Language, Methodology and Applications /
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  Хэвлэсэн: (2020, c2020)
• SystemVerilog for Hardware Description : RTL Design and Verification /
  -н: Taraate, Vaibbhav
  Хэвлэсэн: (2020, c2020)
• Verilog for Example : A Concise Introduction for FPGA Design /
  -н: Readler, Blaine C.
  Хэвлэсэн: (2011, c2011)