RTL Modeling with System Verilog for Simulation and Synthesis : Using System Verilog for ASIC and FPGA Design /
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| Autore principale: | |
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| Natura: | Libro |
| Lingua: | inglese |
| Pubblicazione: |
Tualatin, EUA :
Sutherland HDL,
2017, c2017
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| Soggetti: | |
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