Cita APA (7a ed.)
Sutherland, S. RTL Modeling with System Verilog for Simulation and Synthesis: Using System Verilog for ASIC and FPGA Design. Sutherland HDL.
Cita estilo Chicago (17a ed.)
Sutherland, Stuart. RTL Modeling with System Verilog for Simulation and Synthesis: Using System Verilog for ASIC and FPGA Design. Tualatin, EUA: Sutherland HDL.
Cita MLA (9a ed.)
Sutherland, Stuart. RTL Modeling with System Verilog for Simulation and Synthesis: Using System Verilog for ASIC and FPGA Design. Sutherland HDL.
Precaución: Estas citas no son 100% exactas.