APA način citiranja (7. izdanje)
Sutherland, S. RTL Modeling with System Verilog for Simulation and Synthesis: Using System Verilog for ASIC and FPGA Design. Sutherland HDL.
Čikaški stil citiranja (17. izdanje)
Sutherland, Stuart. RTL Modeling with System Verilog for Simulation and Synthesis: Using System Verilog for ASIC and FPGA Design. Tualatin, EUA: Sutherland HDL.
MLA način citiranja (9. izdanje)
Sutherland, Stuart. RTL Modeling with System Verilog for Simulation and Synthesis: Using System Verilog for ASIC and FPGA Design. Sutherland HDL.
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