RTL Modeling with System Verilog for Simulation and Synthesis : Using System Verilog for ASIC and FPGA Design /
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| Главный автор: | |
|---|---|
| Формат: | |
| Язык: | английский |
| Опубликовано: |
Tualatin, EUA :
Sutherland HDL,
2017, c2017
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MARC
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| 001 | 000439567 | ||
| 005 | 20260624000000.0 | ||
| 009 | 20260713150000.771 | ||
| 020 | |a 978-1-5467-7634-5 | ||
| 037 | |a Acervo ITESO - Biblioteca | ||
| 041 | |a ING | ||
| 082 | |a 621. 392 |b SUT | ||
| 100 | |a Sutherland, Stuart |e (autor) | ||
| 245 | 1 | 0 | |a RTL Modeling with System Verilog for Simulation and Synthesis : |b Using System Verilog for ASIC and FPGA Design / |c S. Sutherland. |
| 264 | 4 | |a Tualatin, EUA : |b Sutherland HDL, |c 2017, c2017 | |
| 300 | |a XXXI, 453 p. | ||
| 336 | |a texto |b txt |2 rdacontenido | ||
| 337 | |a sin mediación |b n |2 rdamedio | ||
| 338 | |a volumen |b nc |2 rdasoporte | ||
| 521 | |a 2022 BO Especialidad en Sistemas Embebidos | ||
| 649 | |a XX | ||
| 650 | |a VERILOG (Lenguaje de Descripción del Soporte Físico) - |x Tema Principal | ||
| 650 | |a Compiladores (Software) | ||
| 650 | |a Lenguaje Ensamblador | ||
| 650 | |a Lenguajes de Programación | ||
| 650 | |a Programación (Software) | ||
| 650 | |a Sistemas Electrónicos | ||
| 650 | |a Ingeniería Computacional | ||
| 650 | |a Ingeniería Electrónica | ||
| 910 | |a Fondo General | ||
| 920 | |a Impresos - Libros | ||
| 930 | |a Colección General | ||
| 905 | |a 101 | ||
| 901 | |a 0500365990 |b IT1 |c ACC |i C177682 |u 20260624 | ||
| 901 | |a 0500365987 |b IT1 |c ACC |i C177683 |u 20260624 | ||
| 902 | |a https://opac.biblio.iteso.mx/vufind/Record/000439567 | ||