Eitemau Tebyg: The Test Access Port and Boundary Scan Architecture /
- SAT-Based Scalable Formal Verification Solutions /
- IEEE Standard Test Access Port and Boundary : Scan Architecture /
- Integrated Circuit Test Engineering : Modern Techniques /
- Digital and Analogue Instrumentation : Testing and Measurement /
- Professional Verification : A Guide to Advanced Functional Verification /
- On-Chip ESD Protection for Integrated Circuits : An IC Design Perspective /
Pwnc: Circuitos Integrados - Prueba y Medición - Tema Principal
- System-on-a-Chip : Design and Test /
- Writing Testbenches : Functional Verification of HDL Models /
- Co-Verification of Hardware and Software for ARM SoC Design /
- Professional Verification : A Guide to Advanced Functional Verification /
- Metodología de cobertura para la validación de circuitos integrados /
- SAT-Based Scalable Formal Verification Solutions /
Pwnc: Circuitos Electrónicos - Prueba y Medición
- Digital Systems Testing and Testable Design / M. Abramovici, M.A. Breuer, A.D. Friedman.
- SAT-Based Scalable Formal Verification Solutions /
- The Test Access Port and Boundary Scan Architecture /
- Neuromodelado de dispositivos electrónicos utilizando perceptrones de tres capas /
- Diseño de un método de prueba de componentes pasivos ensamblados en una tarjeta de circuito impreso /
- Digital and Analogue Instrumentation : Testing and Measurement /