Implementing a TSPC D Flip Flop as an Arbiter for a low power 10-bits 200kS/s ADC with Adaptive Conversion Cycle for High-Quality Audio Applications in 0.18um TSMC CMOS Technology /
Αποθηκεύτηκε σε:
| Κύριος συγγραφέας: | |
|---|---|
| Μορφή: | Thesis Βιβλίο |
| Γλώσσα: | Αγγλικά |
| Έκδοση: |
Guadalajara, México :
edición de autor,
2020
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| Θέματα: | |
| Διαθέσιμο Online: | Ver documento en línea |
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Παρόμοια τεκμήρια: Implementing a TSPC D Flip Flop as an Arbiter for a low power 10-bits 200kS/s ADC with Adaptive Conversion Cycle for High-Quality Audio Applications in 0.18um TSMC CMOS Technology /
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- BandGap Reference Voltage and Serial Communication Module for a Low Power 10 Bits SAR ADC to Biomedical Applications /
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- Optimization of a TSPC D Flip-Flop Using MatLab /
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