SAT-Based Scalable Formal Verification Solutions /
I tiakina i:
| Kaituhi matua: | |
|---|---|
| Ētahi atu kaituhi: | |
| Hōputu: | Pukapuka |
| Reo: | Ingarihi |
| I whakaputaina: |
Nueva York, EUA :
Springer,
2007, c2007
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| Rangatū: | (Series on Integrated Circuits and Systems)
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| Ngā marau: | |
| Ngā Tūtohu: |
Kāore He Tūtohu, Me noho koe te mea tuatahi ki te tūtohu i tēnei pūkete!
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MARC
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| 005 | 20260624000000.0 | ||
| 009 | 20260713143103.822 | ||
| 020 | |a 978-0-387-69166-4 | ||
| 037 | |a Acervo ITESO - Biblioteca | ||
| 041 | |a ING | ||
| 082 | |a 621. 381548 |b GAN | ||
| 100 | |a Ganai, Malay |e (autor) | ||
| 245 | 1 | 0 | |a SAT-Based Scalable Formal Verification Solutions / |c M. Ganai, A. Gupta. |
| 264 | 4 | |a Nueva York, EUA : |b Springer, |c 2007, c2007 | |
| 300 | |a XXIX, 326 p. | ||
| 336 | |a texto |b txt |2 rdacontenido | ||
| 337 | |a sin mediación |b n |2 rdamedio | ||
| 338 | |a volumen |b nc |2 rdasoporte | ||
| 440 | 1 | |a (Series on Integrated Circuits and Systems) | |
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| 650 | |a Circuitos Integrados - |x Proceso de Datos | ||
| 650 | |a Circuitos Electrónicos - |x Prueba y Medición | ||
| 650 | |a Ingeniería Electrónica | ||
| 700 | |a Gupta, Aarti |e (autor) | ||
| 910 | |a Fondo General | ||
| 920 | |a Impresos - Libros | ||
| 930 | |a Colección General | ||
| 905 | |a 101 | ||
| 901 | |a 0500174777 |b IT1 |c ACC |i 000054 |u 20260624 | ||
| 902 | |a https://opac.biblio.iteso.mx/vufind/Record/000287772 | ||