Cita APA (7a ed.)
Taraate, V. SystemVerilog for Hardware Description: RTL Design and Verification. Springer.
Cita estilo Chicago (17a ed.)
Taraate, Vaibbhav. SystemVerilog for Hardware Description: RTL Design and Verification. Singapur: Springer.
Cita MLA (9a ed.)
Taraate, Vaibbhav. SystemVerilog for Hardware Description: RTL Design and Verification. Springer.
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