Cita APA (7a ed.)
Taraate, V. SystemVerilog for Hardware Description: RTL Design and Verification. Springer.
Cita estilo Chicago (17a ed.)
Taraate, Vaibbhav. SystemVerilog for Hardware Description: RTL Design and Verification. Singapur: Springer.
Cita MLA (9a ed.)
Taraate, Vaibbhav. SystemVerilog for Hardware Description: RTL Design and Verification. Springer.
Precaución: Estas citas no son 100% exactas.